yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Add note on docs to clarify verific support
- Yosys seems to handle bit operations on empty strings inconsistently with the original design.
- Wired-or (wor) wires generate $or / $reduce_or cells in output
- No bad property in btor2 file generated from verilog (`write_btor` should error for `$check` cells)
- Docs: Use formatted cmd ref in pdf
- Add support for SystemVerilog's `==?` and `!=?` operators
- Inconsistent simulation before and after yosys synthesis
- Inout can't be read with constant value
- intel_alm: drop quartus support
- export define marco to qtcreator.config
- Docs
- C++ not yet supported