yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- RTLIL::Patch attribute transfer and more
- verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
- [WIP] Rapidflex xt plugin
- arith_tree improvements
- Build on OpenBSD can be smoother
- Migrate build system to CMake
- Bump CI to gcc-16 and fix warnings
- smt2: use canonical SMT names in memory metadata
- [WIP] RapidFlex eFPGA Plugin
- Fix `chparam` values are unsigned when using read_verilog frontend
- Docs
- C++ not yet supported