yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- proc_arst reports misleading "non-constant value 1'm" error for mismatched async-reset polarity
- abc: module and clock domain parallelism, always
- opt_dff → opt_clean cant work
- opt_dff leaves conflicting init attributes on aliased DFF outputs
- Name conflict when using labels inside generate blocks with read_verilog
- `synth_xilinx`: falling-edge BRAM port is unmappable on xc6v/xc7 when the other port needs `READ_FIRST`
- opt_ffinv crashes with std::out_of_range when a multi-bit $not is connected to a 1-bit FF
- opt_ffinv: only treat single-bit $not/$_NOT_ as inverters
- peepopt: reassociate multiply-add chains for DSP inference [sc-814]
- abc_new crashes in wrapped operator flow
- Docs
- C++ not yet supported