yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- plugin Pass cannot override Pass::post_execute()
- Write to the same memory in different always blocks
- write_smt2: bugs caused by the '>>' operator under certain circumstances
- Makefile need not include the -lrt in the Windows machines LDFLAGS
- Crash when using -chparam and '0 as input to a module
- Yosys could not make use of the read_en signal
- Create duplicate GND_NET in one cell
- Synthesis results can change based on comments or blank lines in Verilog source
- Undef propagation in power operator
- gowin: -nolutram needed for simple initialised memory read/write module, otherwise spurious writes corrupt values on startup
- Docs
- C++ not yet supported