yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- `sim` doesn't consider assertions failed if EN=x A=0
- Use /usr/bin/env for bash on remaining places
- synth_nexus with -abc9: CCU2 cells get the low order CIN connected to constant 1'b0
- Error Arises During Synthesis due to Verilog Code Structure
- Async reset inference ignores process switch polarity
- Yosys Verilog Parsing Error: Issue in AST Generation
- Assertion Failure in AST Processing during Verilog Synthesis
- write_cxxrtl: missing parameter when instantiating a Verilog blackbox module.
- tribuf -formal with a single driver of the tristate net connects input to output
- subsicuit $_DFFE_NP_ Issue
- Docs
- C++ not yet supported