yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Registers created by "write_smt2" could be wires by"write_verilog"
- Support for GAL and ATF-series SPLDs
- verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections
- Verific doesn't represent write port priority
- `memory_collect` makes up priority relationships between two `$memwr`
- fmt: Extend string handling for SystemVerilog
- Add an option to synth to enable the booth lower power option
- Add support for unpacked structs
- sim: Add `-assert-cover` option to assert covers were reached
- ABC9 on ice40 causing "ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken"
- Docs
- C++ not yet supported