yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Produced edif gives Multiple Driver Nets error.
- iCE40 DSP inference: Inferred multiply-add not working if parentheses omitted
- Source locations for some elements are missing or off by 1
- Add support for variable cell instance name and type via attribute
- Add support for QuickLogic devices
- rmports doesn't remove unused module output.
- Broken OBUFT inference in submodules
- valgrind issue for `read_verilog -specify` on blackboxes
- Use a proper interface for Verilog source location information
- Appearance of `ifnone` in specify blocks crashes Verilog frontend
- Docs
- C++ not yet supported