yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- read_verilog gives multiple drivers to variables initialized both in declaration and initial
- Preservation of signedness flag on attribute values inconsistent
- techmap should warn when CONSTMSK/CONSTVAL are used with a nonexistent port
- `cxxrtl` output port changes value after back to back `.step()`
- proc_dff: bit-granularity optimizations and refactoring
- Add Optimization Barriers
- Rename techmap
- Measure global_id_index_ construction overhead
- `write_verilog` does not replace bwmux instances
- muxcover generates x states
- Docs
- C++ not yet supported