yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- opt_mem pass is not respecting (* keep *)
- write_verilog: Vivado transparent memory port regression
- Interface synthesis bug: Logic missing from main evaluation path ?
- equiv_* passes do not work well with abc
- ABC doesn't retime when _DFF_PP1_ cells are used, but does retime when _DFF_P_ cells are used
- Module-level parallelism
- proc_mux: use assignment action locations for mux src
- `proc_prune` undefines connections / incorrect scheduling semantics optimisation
- docs: touch up contributing guidelines
- BRAM initialization error
- Docs
- C++ not yet supported