yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- read_verilog: conflicting drivers for integers set in multiple processes
- int overflow causes `Const` ctor to throw length_error
- cxxrtl: -O1 optimisation unbuffers wires too permissively
- Selection syntax doesn't understand escaping
- opt_dff: skip convertion to dffe for keep wires
- Add aldff splitting to avoid logic data loops
- verific: add -optimization option
- opt_mem pass is not respecting (* keep *)
- Interface synthesis bug: Logic missing from main evaluation path ?
- equiv_* passes do not work well with abc
- Docs
- C++ not yet supported