yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Multiple edge sensitive events found for this signal!
- Yosys hangs indefinitely when executing `read_aiger -xaiger` after `abc9` in `synth_intel_alm` flow
- Hang during synthesis: Yosys enters an infinite loop during $dffe enable generation (or other pass), with no termination.
- fminit causes std::out_of_range
- FSM extraction for FSMs with asynchronous reset
- Let opt_dff combine flops with arbitrary forms of equivalent logic
- Verific SVA FSM size error needs more info
- Make async flip flops easy to opt with new $priority cell
- fsm_expand deleting design if state register is not initialised
- equiv_opt falsely claims equivalence on designs with different unknown modules
- Docs
- C++ not yet supported