yosys
https://github.com/cliffordwolf/yosys
C++
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- Issues
- Don't sort anything ever
- Support mixed input/output in cutpoint handling of inout
- Unify handling of quoted strings in pass args
- autoname may be inefficient for large circuits
- Add parsing of verilog module port renaming (aliases)
- Less wasteful CellTypes usage in opt_clean
- Unify make test and make unit-test
- Document and regression-test staged/cosimulation-based verification
- abc: add -word mode which uses word-level cells where possible
- feature breakreduce
- Docs
- C++ not yet supported