yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- signorm: directed RTLIL, incremental optimization
- Regression: "ERROR: Don't know how to detect sign and width for AST_AUTOWIRE node!"
- read_verilog -sv crashes with internal assert on malformed input (empty if-body + declaration)
- abc: remove -fast (again)
- Feature request: allow using a reset signal to derive post-reset initial states
- verilog frontend/backend: Fix multiple signedness issues
- functional error in the edif generated by the serial port program.
- `chparam` values are unsigned when using `read_verilog` frontend
- opt_expr: Respect keep attribute for double-inverter folding
- opt_dff unsound init handling assumes opt_clean
- Docs
- C++ not yet supported