yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Fix: `read_verilog` doesn't respect `signed` keyword
- muxpack: fix chaining
- Verilog backend struggles with multidimensional array indices into array dimensions from Verific frontend that are non-PoT and/or don't start from zero
- PR #5876 causes build errors when `YOSYS_ENABLE_PYTHON` is specified
- verilog backend: preserve `signed` on wire and port declarations
- the documentation for the `--dont_use` argument for the `abc` pass is just a copy/paste of another
- always_latch incorrectly tries to latch address of an array
- Incorrect Netlist Transformation in muxpack Pass
- clockgate: support $sdffe properly
- help with hierarchy: refactor
- Docs
- C++ not yet supported