yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- verilog: fix `**` associativity to right per IEEE 1364-2005 / 1800-2017
- chores: Fix mixed spaces vs tabs
- yosys/abc assertion with OpenROAD-flow-scripts asap7/riscv32i-mock-sram
- Verilog frontend: `'{default: ...}` assignment pattern is a syntax error
- verilog: support '{default: ...} assignment patterns for unpacked arrays
- `tribuf`: infer tri-state nested behind a mux
- ast: guard against module name collision during reprocessing
- gatemate: fix CC_FIFO_40K sim for non 2^n width usages
- `synth_xilinx` DSP packing asserts (crashes) on a non-zero-init input register
- gowin: infer DSP multiply-accumulate for the GW5A family
- Docs
- C++ not yet supported