yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- No support for Verilog-2001 non-ANSI port aliases
- Allow loading plugins "by name" from more than one source (alt: add a search path for plugins)
- CXXRTL RFE: better debug messages for out-of-bound memory access
- CXXRTL: Strange timings and mismatch in dumped VCD
- Intel le
- SMT2 Backend Treats Non-POT-Sized Memories as next higher POT
- The 'design' command does not clear context as expected
- make test results in Test: arrays02 -> ERROR!
- iCE40 DSP inference creates technically-unsupported configurations
- Segfault during 'write_aiger' with simple logic loop `assign x = x & x`
- Docs
- C++ not yet supported