yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Suboptimal default synthesis of `$bmux`, `$shiftx`
- Inconsistency Issue with Continuous Assignment Error after FSM Optimization using opt_dff and Other Passes
- Support for more series of anlogic FPGAs
- Produce `$bmux` cells in shiftmul transformation
- Added nordshift attribute
- Warnings for missing backticks
- nlatch Verliog code synthesis question
- Liberty front end doesn't properly parse boolean expressions
- Improve write_verilog speed
- How to figure out the actual name of the flipflop in yosys?
- Docs
- C++ not yet supported