yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- sim: Evaluate all cells once
- [abc] Assertion src/base/abc/abcAig.c:1134: void abc::Abc_AigUpdateLevelR_int(abc::Abc_Aig_t *): Assertion `Abc_ObjIsNode(pNode)' failed.
- Split off evaluable/combinational flags in `celltypes.h`
- Multiple edge sensitive events found for this signal
- Can't find object for defparam
- gowin: add mux techmap and whitebox
- Confusing error message when using default_nettype none and a local is defined in unnamed block in verilog mode
- Assertion fail with chparam.
- Improved `sim` handling of `$display`/`$print`
- check: Un-sigmap the `check` command
- Docs
- C++ not yet supported