yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Reduce compiler warnings when building yosys
- read_verilog does not accept module port lists with .port_identifier
- segfault in proc_dlatch when latch is driven by conflicting drivers
- Add tri-state support for const eval and add tribuf -propagate option
- Assert `flow.wire_comb_defs[it].size() == 1` in `write_cxxrtl`
- `sta` command hangs on some designs
- `tee -q -o <bad-path>` fails silently
- log_deprecated
- abc segfaults in certain usecase
- Synthesis fails on MacOS but succeeds on Linux (possibly ABC error)
- Docs
- C++ not yet supported