yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- read_verilog -sv crashes with internal assert on malformed input (empty if-body + declaration)
- Feature request: allow using a reset signal to derive post-reset initial states
- opt_expr: Respect keep attribute for double-inverter folding
- opt_dff unsound init handling assumes opt_clean
- proc_mux: avoid redundant mux cells for full_case switches with a dominant arm value
- dfflibmap: pass selection to dfflegalize
- async2sync: inherit src attributes on new_q and new_d wires
- Yosys EXTRACT_FA crash: consteval.h:83 assertion failed when extracting adders from flattened design
- User control over async flop inference
- BUFNORM pass crashes with std::out_of_range in dict::at() when processing latch with undriven/undefined signals
- Docs
- C++ not yet supported