yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- chores: Fix mixed spaces vs tabs
- yosys/abc assertion with OpenROAD-flow-scripts asap7/riscv32i-mock-sram
- `tribuf`: infer tri-state nested behind a mux
- ast: guard against module name collision during reprocessing
- gatemate: fix CC_FIFO_40K sim for non 2^n width usages
- README: cmake build and test instructions
- gowin: infer DSP multipliers for the GW5A family
- Assertion in hierarchy when elaborating parameterized generate instances due to non-unique name
- Propagate src attributes in opt_share
- Performance issue for read_verilog of nested for-loops with intermediate wire declaration
- Docs
- C++ not yet supported