yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- rtlil: remove dead verilog bindings
- liberty_cache: per user SCL cache directory [sc-843]
- Adding error cases to formal backends for invalid formal cells
- Run ABC for each module in parallel
- opt_dff: avoid quadratic sigmapping in mux tree feedback search [sc-839]
- synth*: run check after proc before opt_clean to discover process-ini…
- check: detect process-driver conflicts
- Gowin SPX9 BSRAM returns wrong synchronous-read data when read output is cleared while idle
- Fails to substitute module code for instance in particular situations
- Add AI policy
- Docs
- C++ not yet supported