yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- aiger2: remove $input_port cells when leaving bufnorm
- `$(yosys-config --datdir)/plugins` does not give true module loading path
- wit2yw throws away the per-step values of $anyseq, so BTOR counterexamples do not replay
- read_verilog: `` token pasting breaks when a macro argument is preceded by a newline or a comment
- Fix concatenation of short and init-only witness traces
- cmake: do not alter name in yosys_python_executable
- Dynamic right shift followed by logical-not is synthesized incorrectly
- select: alias wires don't count for cone depth
- logger: add LogSourceLocation
- multiple constant multiplication (mcm) pass
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- C++ not yet supported