yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- xilinx/cells_sim.v: read_slang rejects the specify blocks (106 errors)
- Restrict `iopadmap` in `synth_gatemate` to top so `keep_hierarchy` and `-noflatten` work properly
- ERROR: Reached unsupported cell CCU2C
- verific SVA import: `disable iff` discharges an attempt that already completed (reset in the next cycle masks assert/assume violations)
- [abc] Assertion fails in abc_ops_reintegrate.cc
- [abc] command yosys-abc -s -f abc.script 2>&1 returns -2
- Verilog attribute documentation should be scoped to user-facing verilog features
- Support reals used as a condition
- Support reals in constant functions
- synth_xilinx DSP register absorption corrupts a signed product output
- Docs
- C++ not yet supported