yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- stat -tech cmos estimates a $_BUF_ cell as 1 transistor
- `write_btor`: a one-entry memory (zero-width address) is written as invalid BTOR2 (`uext <sid> -1 1` after `memory_map`, `sort bitvec 0` and `read ... -1` as an array)
- `read_verilog -sv`: a size cast of a constant operand folds the operand at its self-determined width, then extends it
- `read_verilog -sv`: the result width of a size cast leaks the operand's width into the enclosing expression
- abc_new: a "-script" anywhere in the arguments, such as in a liberty path, disables the default script
- NetView [sc-960]
- cells_xtra.v has the wrong default for IBUFDS_GTE2.CLKSWING_CFG ("TRUE" instead of 2'b11)
- xilinx/cells_sim.v: read_slang rejects the specify blocks (106 errors)
- ERROR: Reached unsupported cell CCU2C
- verific SVA import: `disable iff` discharges an attempt that already completed (reset in the next cycle masks assert/assume violations)
- Docs
- C++ not yet supported