yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- readmem[hb] spuriously called with module parameter default value
- synth_ice40 -dsp crashes when SB_MAC16 is manually instantiated
- Feature request: SystemVerilog static casts
- Verilog backend: pack identical signals in concatenation
- cxxrtl blackbox behavior issue / possible bug ?
- Initial block with $readmemh ineffective with Lattice ECP5-25F FPGA
- `autoname` memory usage very high with CPU generated from `ghdl-yosys-plugin`.
- cxxrtl: Verilog frontend's handling of `$meminit` breaks a lot of assumptions
- CXXRTL doesn't approach steady state on O4 when routing signal via module
- In CXXRTL edge eval is before calculating value
- Docs
- C++ not yet supported