yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- `read_verilog` never completes and continues to grow system memory usage
- CXXRTL should warn or fail on unsupported clock features
- Support for multi-line string for system verilog
- Yosys will sometimes emit a flip-flop that never toggles instead of a constant 0
- Fail to detect FSM with specific writing style
- enforce that hdlname/scopename is used consistently with public/private names
- Add an optional yosys start script
- synth_xilinx error in simple demo
- Deviation Between Yosys RTLIL EBNF Docs and RTLIL Lex/Yacc Frontend
- Synthesis with -nowidelut gives drastically better results
- Docs
- C++ not yet supported