yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Derive abstract cells in top module during hierarchy
- Wrong error message mentioning defparam when overriding localparam
- Update contributing rst with command/cell help info
- Support user-defined primitives in the Verilog frontend and RTLIL
- share: replace activation patterns with more SAT
- share: limit SAT effort
- Optimization shouldn't depend on ordering of registers when flattening is enabled
- File references in docs should link to file on git
- Add selectors for cell type properties
- Optimize opt_expr evaluation ordering
- Docs
- C++ not yet supported