yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Verific SVA FSM size error needs more info
- Add -nocells flag to equiv_make and equiv_opt
- Make async flip flops easy to opt with new $priority cell
- Setundef doesn't respect selection
- ABC9 is replacing missing ports with ports connected to 0, breaking Nexus carry chains
- sat: dff output changes without clock edge
- keep_hierarchy Verilog attribute leading to unconstrained top level ports from internal signals
- Parallelize `opt_clean` pass
- fsm_expand deleting design if state register is not initialised
- equiv_opt falsely claims equivalence on designs with different unknown modules
- Docs
- C++ not yet supported