yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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Help out
- Issues
- Verific SVA FSM size error needs more info
- Add -nocells flag to equiv_make and equiv_opt
- Make async flip flops easy to opt with new $priority cell
- ABC9 is replacing missing ports with ports connected to 0, breaking Nexus carry chains
- fsm_expand deleting design if state register is not initialised
- equiv_opt falsely claims equivalence on designs with different unknown modules
- failure in yosys-abc with return code 134
- False-positive proc_arst detection leads to strange situations
- Support ifnone in Verilog specify blocks
- Cross-OS Determinism
- Docs
- C++ not yet supported