yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- equiv_induct: error on missing model
- Wide mux cells ($_MUX4_ et al) are incorrectly marked as evaluable
- Multiple edge sensitive events found for this signal!
- Yosys hangs indefinitely when executing `read_aiger -xaiger` after `abc9` in `synth_intel_alm` flow
- Hang during synthesis: Yosys enters an infinite loop during $dffe enable generation (or other pass), with no termination.
- fminit causes std::out_of_range
- FSM extraction for FSMs with asynchronous reset
- Unify info about make test and make unit-test
- Let opt_dff combine flops with arbitrary forms of equivalent logic
- add breaksop feature
- Docs
- C++ not yet supported