yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- autoname may be inefficient for large circuits
- Add parsing of verilog module port renaming (aliases)
- Logic loop for asynchronous partial reset trigger
- RFC: upstream verific -optimization option
- Integrate fuzzing doc into public docs
- aigerparse: process user LUTs first to work around occasional abc ordering issues
- dfflibmap violates selection through dfflegalize
- Yosys error message does not provide information about the location of the error.
- Create functions that can be called from anywhere to turn `linux_perf` on or off
- Wide mux cells ($_MUX4_ et al) are incorrectly marked as evaluable
- Docs
- C++ not yet supported