yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Add Carry-save adders
- `chparam` values are unsigned when using `read_verilog` frontend
- opt_expr: Respect keep attribute for double-inverter folding
- opt_dff unsound init handling assumes opt_clean
- proc_mux: avoid redundant mux cells for full_case switches with a dominant arm value
- dfflibmap: pass selection to dfflegalize
- async2sync: inherit src attributes on new_q and new_d wires
- abc: new option to pass extra ABC read_lib args
- Yosys EXTRACT_FA crash: consteval.h:83 assertion failed when extracting adders from flattened design
- User control over async flop inference
- Docs
- C++ not yet supported