yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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Help out
- Issues
- Fixed typos and incorrect grammar
- aig-related cleanup [sc-269]
- read_verilog -sv crashes with internal assert on malformed input (empty if-body + declaration)
- abc: remove -fast (again)
- Synthesis non-determinism due to design objects order
- Feature request: allow using a reset signal to derive post-reset initial states
- verilog frontend/backend: Fix multiple signedness issues
- syn fail
- Update tests and test infrastructure
- functional error in the edif generated by the serial port program.
- Docs
- C++ not yet supported