yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- xilinx_dsp: do not absorb nonzero sync-load constants into RSTM/RSTP
- verilog: fix `**` associativity to right per IEEE 1364-2005 / 1800-2017
- chores: Fix mixed spaces vs tabs
- yosys/abc assertion with OpenROAD-flow-scripts asap7/riscv32i-mock-sram
- Verilog frontend: `'{default: ...}` assignment pattern is a syntax error
- verilog: support '{default: ...} assignment patterns for unpacked arrays
- log rewrite [sc-748]
- opt_dff -sat: cleanup and refactor [sc-725]
- tests: Explicitly run tests without and with Verific where applicable
- `tribuf`: infer tri-state nested behind a mux
- Docs
- C++ not yet supported