yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Fix Spartan-6 SDP BRAM width mapping
- Failed to rename *.scl.tmp to *.scl falling back to liberty format
- `write_smt2`/`write_btor` silently ignore `$live`/`$fair`
- Read Verilog Hangs with Memory Leak with Recursive Macro
- Slowness in opt_dff dff -> dffe conversion
- rmports: remove output ports unused by all instances [sc-799]
- liberty: add filtering for things we need
- twines: rich interned strings
- hdlname is lost through synthesis -- cells can't be traced back to RTL
- proc_mux: avoid repeated work in mux tree construction
- Docs
- C++ not yet supported