yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
Triage Issues!
When you volunteer to triage issues, you'll receive an email each day with a link to an open issue that needs help in this project. You'll also receive instructions on how to triage issues.
Triage Docs!
Receive a documented method or class from your favorite GitHub repos in your inbox every day. If you're really pro, receive undocumented methods or classes and supercharge your commit history.
C++ not yet supported3 Subscribers
Add a CodeTriage badge to yosys
Help out
- Issues
- Read Verilog Hangs with Memory Leak with Recursive Macro
- hdlname is lost through synthesis -- cells can't be traced back to RTL
- proc_mux: avoid repeated work in mux tree construction
- xilinx_dsp: do not absorb nonzero sync-load constants into RSTM/RSTP
- chores: Fix mixed spaces vs tabs
- yosys/abc assertion with OpenROAD-flow-scripts asap7/riscv32i-mock-sram
- Verilog frontend: `'{default: ...}` assignment pattern is a syntax error
- `tribuf`: infer tri-state nested behind a mux
- ast: guard against module name collision during reprocessing
- gatemate: fix CC_FIFO_40K sim for non 2^n width usages
- Docs
- C++ not yet supported