yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Add missing blackboxes where appropriate
- Unexpected module mixing in BTOR2 output depending on RTL module ordering
- add `MUX32` cells
- `$(yosys-config --datdir)/plugins` does not give true module loading path
- wit2yw throws away the per-step values of $anyseq, so BTOR counterexamples do not replay
- Fix concatenation of short and init-only witness traces
- select: alias wires don't count for cone depth
- opt_dff → opt_clean cant work
- opt_dff leaves conflicting init attributes on aliased DFF outputs
- Name conflict when using labels inside generate blocks with read_verilog
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- C++ not yet supported