yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- celltypes: compile-time lookup tables for internal cells
- `log_id_cache` memory leaks are problematic
- Yosys is unable to prove logical equivalence when _DFFE_PP_ cells are duplicated
- Add verific -set interface for Yosys-Verific settings
- Logging: Add log sink system to replace ostreams
- CMake: Rebase From Main & Tests Working
- ANSI-style modules from write_verilog
- `ERROR: Assert sig_macc.count(n->y) == 0 failed` occurs when multiple `$add` cells drive the same signal.
- Inconsistent 'x handling in opt_expr for muxes
- A `core dumped` occurred during the `synth_microchip` process when executing the `MICROCHIP_DSP` pass.
- Docs
- C++ not yet supported