yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- `ERROR: Assert 'signal_list[id1].bit.wire != nullptr'` occurred during the `synth_efinix`
- A core dump occurred during the `synth_coolrunner2` process.
- The `synth_efinix` synthesis process keeps `Adding EN signal` and does not terminate.
- muxcover pass stalls if $_MUX_ output is disconnected
- yosys-abc: src/map/scl/sclLibUtil.c:77: void abc::Abc_SclHashCells(SC_Lib *): Assertion `*pPlace == -1' failed.
- An infinite loop occurred in the log during the `synth_greenpak4` process.
- Test coverage of `opt_expr` is only 21.5%
- Trigger abc segfault for testing
- Don't evaluate $finish cells during read_verilog
- QuickLogic DSPv2 support
- Docs
- C++ not yet supported