yosys
https://github.com/cliffordwolf/yosys
C++
Yosys Open SYnthesis Suite
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- Issues
- Gowin SPX9 BSRAM returns wrong synchronous-read data when read output is cleared while idle
- Fails to substitute module code for instance in particular situations
- Add AI policy
- Fix Spartan-6 SDP BRAM width mapping
- Read Verilog Hangs with Memory Leak with Recursive Macro
- rmports: remove output ports unused by all instances [sc-799]
- twines: rich interned strings
- hdlname is lost through synthesis -- cells can't be traced back to RTL
- proc_mux: avoid repeated work in mux tree construction
- xilinx_dsp: do not absorb nonzero sync-load constants into RSTM/RSTP
- Docs
- C++ not yet supported